I/O buffers are used to drive the external pins of integrated circuits. In general, I/O buffers must be capable of sourcing and sinking large amounts of current in order to meet standard specifications and to drive capacitive loads quickly. However, if an I/O pin were to become shorted either to ground, a voltage supply or another pin for more than a few tenths of a second, the integrated circuit may be irreversibly damaged.
If the integrated circuit is a field programmable gate array (FPGA) which can be programmed to implement a wide variety of logic circuit designs, the problem is particularly severe because short circuits may be caused simply by loading the wrong device configuration pattern. The most common failure in an FPGA arises from "pin contention," where two or more driver circuits are each driving the same board trace but one (or more) is (are) driving a logic high while the other(s) is (are) driving a logic low. If this condition lasts only a few tens of microseconds, there will not be any harm done. However, if the condition persists for several milliseconds, the temperature of the I/O buffer rises to a dangerous level and parasitic bipolar circuit elements in the I/O buffer may begin to conduct. If one of these parasitic bipolar elements goes into second bipolar breakdown (current hogging) then the concentration of power dissipation in a very small region results in permanent thermal damage to the I/O buffer.
Therefore, while it is desirable to be able to limit current, most I/O buffers do not do so because of the difficulty in directly measuring current through a CMOS transistor.
It is accordingly an object of this invention to provide an indirect yet simple method of detecting an overcurrent condition by comparing input and output voltage levels and limit output current accordingly.
It is a further object of this invention to determine if an overcurrent error condition exists by monitoring this overcurrent detection for a predetermined period of time, with or without the use of an external clock signal.
It is a further object of this invention to provide a mechanism for limiting the output current if the overcurrent error condition exists.
It is still further an object of this invention to provide a means of controlling the overcurrent circuitry and signaling the occurrence of an overcurrent error condition.